Thursday, August 11, 2016

4 Challenges in 16nm Nodes and How to Overcome Them

With technological advances happening at lightning fast speed, VLSI engineering has picked up immense steam in the last couple of years. Semiconductor companies today are under immense pressure to design and develop integrated circuits that meet the distinct needs of products across a diverse range of industries.
As device modernization takes over the world, SoC tapeouts and ASIC, FPGA design has become more important than ever. This has led companies to offer a host of design services: from feasibility study, architecture definition, RTL coding and floor-planning to SoC integration and IP development. Expertise around IPs, EDA tools, packaging and product engineering enable first-time-right silicon. In addition, close collaboration between design, testing, packaging, and process engineering teams results in high yield products.

Enhanced Performance Using 16nm
The 16nm fabrication node has transformed the semiconductor design industry. While traditional transistors have two dimensions (length and width) that control the current and voltage characteristics of a device, the 16nm node adds a third dimension (height) allowing semiconductor designers to increase the current drive capability by adding more fins and adjusting the height. This leads the 16nm to have better electrostatic control over the channel, resulting in substantial leakage improvements. This combination of reduced leakage and increased drive capability enables semiconductor devices to have enormous performance advantages in addition to reduced power consumption and minimized costs as compared to older, traditional nodes.
Looming Challenges

 

As the embedded hardware device services industry rapidly adopts the 16nm technology, chip designers are faced with a host of challenges. To keep up with the technological upheavals, the 16nm has introduced several alterations in the way the devices are fabricated and how circuits are built. Although the new node offers extraordinary improvements in terms of high circuit speed, low leakage and enhanced density, there are several challenges with respect to design, electromigration, electrostatic discharge and thermodynamics:
The Design Challenge: Like any new technology, 16nm nodes pose some design challenges. As performance of 16nm nodes can be increased only by adding more fins, it can be done only in increments; where as in standard design, designers had the freedom to modify the width based on their requirement. Also, due to the unique nature of the circuit, the FinFET structure tends to have higher parasitic capacitance that adds complexity to the layout extraction and also limits speed. Designers must carefully study the resistors and capacitors inside the transistor, including local interconnects, fins and gates in order to predict device behavior.
The Electrostatic Discharge Challenge: Another challenge with the 16nm node is with respect to electrostatic discharge. The increased current density causes the device to heat up more quickly compared to traditional nodes, reducing the electrostatic discharge protection degree. As the breakdown voltages for 16nm nodes are much lower, they decrease the electrostatic discharge window. To overcome this challenge, designers need to use a simulation driven approach to carefully and accurately place components onto the circuit.
The Electromigration Challenge: The increase in current density per unit area brings with it the challenge of electromigration; as more current flows through device, the margins for electromigration become smaller, and meeting the Mean Time to Failure requirements becomes more challenging. To achieve accuracy, new methods that are dependent on the direction of current flow and circuit topology need to be adopted.
The Thermodynamics Challenge: As higher current passes through the circuit with 16nm nodes, there is a higher likelihood of interconnect failure and metal burn-out due to current overflow. Heat escape pathways in FinFET devices are not as good, increasing the probability of self-heating. Performing current density checks during the design stage accurately identifies and resolves the current bottlenecks and ensures interconnect safety. In addition, accurate modelling of localized heat sources ensure the optimum thermal distribution.

Overcoming Challenges
Since the 16nm node enables semiconductor companies to achieve substantial performance and cost benefits, mature VLSI processes and checklists will help companies execute complex IC design projects to develop products across networking, consumer devices, automotive, smartphones, multimedia, aerospace, servers, automated test equipment, and MEMS. Proficiency in Verification IPs (VIPs) and expertise on EDA tool chains and hands-on experience with FPGA devices will drive the industry forward.



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